Hardware Constructions for Error Detection in Lightweight Welch-Gong (WG)-Oriented Streamcipher WAGE Benchmarked on FPGA
Jasmin Kaur, Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh
Abstract
Providing an acceptable level of security at low cost becomes a challenge in embedded systems that have limited resources, e.g., the devices used in the Internet of Things applications. Lightweight cryptography aims to overcome this challenge by adopting security measures which are well suited for resource-constrained usage models. As we move towards standardizing the approach for lightweight cryptography, several cipher implementations were proposed to NIST, out of which WAGE is one of the algorithms advanced to the next round. WAGE is a 259-bit lightweight stream cipher that derives its cryptographic properties from the WG stream cipher and is designed to provide Authenticated Encryption with Associated Data (AEAD) in hardware implementation. In this paper, the error detection schemes for the nonlinear sub-blocks of WAGE cipher have been presented for reliable implementations of the cipher on hardware. The signature-based error detection schemes presented in this paper are platform oblivious. Derivations for signature and interleaved signature schemes for both logic- and LUT-based implementations are presented for the 7-bit S-Box and Welch- Gong permutation (WGP) of WAGE. The presented schemes are evaluated for error coverage and are benchmarked on field-programmable gate array (FPGA) to show acceptable overheads and practical error coverage.