A 0.2-V 10-Bit 5-kHz SAR ADC With Dynamic Bulk Biasing and Ultra-Low-Supply-Voltage Comparator
Alexander Petrie, Yixin Song, Whitney Kinnison, Yong Qu, Kent Layton, Shiuh-Hua Wood Chiang
Abstract
This paper describes a 10-bit 5-kHz SAR ADC under an ultra-low-supply-voltage of 0.2 V for low-power applications. To tolerate the severe variations in the subthreshold regime, a novel dynamic bulk biasing circuit senses the NMOS/PMOS strength ratio in the background and applies feedback to equalize the strengths to maintain the circuit functionality. A rigorous analysis examines the dynamics and convergence of the proposed biasing circuit in the time- and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$z$ </tex-math></inline-formula> -domains. A new comparator relaxes the stringent speed-noise trade-off under the 0.2-V supply. Employing switched ac-coupling, stacked input pairs, and voltage-boosted load capacitors, the comparator achieves more than a threefold improvement in speed with little noise penalty. The DAC implements grouped capacitors with quantized sub-radix-2 scaling for redundancy and low power and achieves 10-bit matching. Details of the complete ADC design are described. The measured ADC consumes 22 nW and exhibits a peak DNL and INL of 0.45 LSB and 0.67 LSB, respectively. The measured SFDR and SNDR at Nyquist are 70.6 dB and 52.8 dB, respectivley, yielding an FoM of 12.3 fJ/conv.-step. Measurements show the dynamic bulk biasing compensates the N/P strength ratio variations to optimize the SNDR. We also show that the proposed dynamic bulk biasing successfully maintains the ADC performance over supply variations and improves the yield by nearly twofold over 20 chips.