A Closed-Loop Neuromodulation Chipset With 2-Level Classification Achieving 1.5-Vpp CM Interference Tolerance, 35-dB Stimulation Artifact Rejection in 0.5ms and 97.8%-Sensitivity Seizure Detection
Yuwei Wang, Hongrui Luo, Yang Chen, Zihao Jiao, Quan Sun, Lei Dong, Xinlei Chen, Xiaofei Wang, Hong Zhang
Abstract
This work presents an 8-channel closed-loop neuromodulation chipset with 2-level seizure classification. The power-consuming fine classifier is only enabled when the coarse classifier in the frontend chip judges the patient's status as “suspected seizure”. This scheme can reduce the overall power consumption extensively since seizure usually occurs with very low possibility. In the capacitive-coupled instrument amplifier (CCIA) of the front-end IC, a feedback based common-mode (CM) cancellation circuit is proposed to suppress large-scale CM interferences and the stimulation artifacts are suppressed by a mixed-signal loop with fast response. An auto-zero based pre- charge path is adopted to boost the input impedance, while the electrode DC offset is canceled by a DC servo loop with very-large and accurate time constant. The 2.32-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> front-end chip and 3.51-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> DSP chip implemented in 0.18 μm CMOS are applied in a deep-brain stimulation (DBS) neuromodulator. Measurement results show that the CCIA can suppress 1.5-Vpp CM interference, and achieve an accurate high-pass corner frequency as low as 0.1 Hz and an input impedance greater than 2.2 GΩ. The overall classifier achieves 97.8% sensitivity and consumes only 1.16-μW average power for the CHB-MIT database test. The chipset has been verified by in vivo measurement, showing that the stimulation artifact can be suppressed by 35 dB within 0.5 ms.