First Demonstration on the Transient Writing Characteristics of Multi-bit ALD IGZO 2T0C DRAM by Fast I-V Measurement
Liankai Zheng, Ziheng Wang, Zhiyu Lin, Mengwei Si
Abstract
In this work, we investigate the transient characteristics during the multi-bit writing operation of the 2T0C DRAM by ALD IGZO transistors. It is found there are three main mechanisms that contribute to the transient voltage drop on storage node (VSN) after data writing, including capacitive coupling, mobile charge sharing and trapped charge releasing. A mathematical model is built to decouple the impact of different mechanisms, which fits well with the experimental data. The data crosstalk caused by trapped charge releasing effect is identified as the major challenge for the multi-bit operation of IGZO 2T0C DRAM. By optimizing the interface of gate insulator and IGZO and adopting a proposed new writing strategy with non-linear data levels, the 4-bit 2T0C DRAM without data crosstalk is achieved with low standard deviation on read current.