Clarifying the Role of Ferroelectric in Expanding the Memory Window of Ferroelectric FETs with Gate-Side Injection: Isolating Contributions from Polarization and Charge Trapping
Yixin Qin, Saikat Chakraborty, Zijian Zhao, Kijoon Kim, Suhwan Lim, Jongho Woo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Xiao Gong, Asif Islam Khan, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni, Kai Ni
Abstract
In this work, we performed a comprehensive experimental and modeling study, clarifying the role of ferroelectric materials in boosting the memory window of FeFETs with gate-side charge injection for the first time. We separated the ferroelectric contributions to the memory window into remnant polarization and top charge trap layer (CTL) trapping. Our findings demonstrate that: (i) Ferroelectric materials enhance the memory window in two ways: by switched more polarization when CTL traps more, which provides screening charges, and through their super-linear Q-V relationship that boosts the CTL electric field and enhances charge trapping; (ii) The contributions from polarization and CTL trapping mutually reinforce each other, resulting in a larger memory window compared to a ferroelectric + dielectric stack or a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{high}-\kappa+$</tex> CTL stack, where only one factor is active; (iii) Combined experimental data and TCAD simulations confirm that approximately one-third of the memory window is due to increased polarization, while two-thirds result from CTL trapping; (iv) The memory window can be further enhanced with a blocking oxide on top of the CTL, achieving up to a 16V window with an ONO blocking oxide.