Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

Nibedita Karmokar, Arvind Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar

2023IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems12 citationsDOI

Abstract

Process variations and the effect of interconnect parasitics can cause significant perturbations in the performance metrics of capacitive digital-to-analog converters (DACs). This article develops fast constructive procedures for common-centroid placement and routing for binary-weighted and split capacitor array topologies of charge-sharing DACs. Our approach particularly targets FinFET technologies with high wire and via parasitics: in these technology nodes, we show that the switching speed of the capacitor array, as measured by the 3-dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for both binary-weighted and split DACs, to optimize the switching speed. A balance between 3-dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

Topics & Concepts

Parasitic extractionConvertersCapacitorCentroidRouting (electronic design automation)Electronic engineeringComputer scienceBinary numberTopology (electrical circuits)Network topologyElectrical engineeringVoltageEngineeringMathematicsComputer networkArithmeticArtificial intelligenceAnalog and Mixed-Signal Circuit DesignLow-power high-performance VLSI designAdvancements in Semiconductor Devices and Circuit Design