7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and −54.4dBc Spurs Under 50mV Supply Noise

Abstract

A low-jitter multi-phase clock generator is pivotal in high-speed serial link transceivers. With data rates surpassing 100Gb/s, incorporating sub-rate operations becomes essential to overcome inherent bandwidth constraints. This, in turn, demands the generation of multiple sub-rate clock phases. However, the difficulty lies in producing these clock signals with minimal jitter, particularly at high frequencies (>10 GHz). Contemporary clock generators with integrated jitter below $100\mathrm{fs}_{\mathrm{rms}}$ primarily utilize LC oscillators [1]. However, LC-based phase-locked loops (PLLs) occupy considerable space, lack efficiency in generating multiple phases, and are vulnerable to electromagnetic coupling in multi-lane SerDes systems. In contrast, ring-oscillator (RO) based architectures offer a compact footprint and inherent suitability for multi-phase clock generation. As a result, there is a growing need for resilient RO-based PLLs that can achieve jitter levels comparable to those of LC-based alternatives. However, the performance of these PLLs is hindered by excessive noise inherent to the RO, a challenge further exacerbated by the requirement to function within noisy supply environments and across a wide temperature range. Prior investigations [2–4] have recognized this limitation and focused on widening the RO phase noise suppression bandwidth. To illustrate, an injection-locked PLL was employed to extend the bandwidth to approximately one-sixth of the reference frequency $(\mathrm{F}_{\mathrm{REF}})$ in [2]. These techniques, while effective, necessitate intricate frequency-tracking loops that prove challenging to implement while aiming for low jitter across a wide frequency range. An alternate approach detailed in [4] accomplished 135fs jitter but relied on an $\mathrm{F}_{\mathrm{REF}}$ of 1.85GHz, yielding a modest 7GHz output. Recent trends have seen sampling PLLs emerge, lessening the noise concerns inherent to traditional PLLs [1]. Nevertheless, achieving <100 fs jitter performance and >10 GHz output using an RO remains elusive. Given these limitations, this paper presents an 8-phase sampling PLL that operates from 6.8GHz to 14GHz $(2 \times$ higher output frequency compared to [4]) and achieves an integrated jitter of 69.3fs (one-third of the jitter reported in [2]), an in-band noise level of −131.4dBc, and a spur level below −54.4dBc under 50mV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</inf> supply ripple.

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