Interface Compensation for More Accurate Power Transfer and Signal Synchronization within Power Hardware-in-the-Loop Simulation
Zhiwang Feng, Rafael Peña‐Alzola, Paschalis Seisopoulos, Mazheruddin Syed, Efrén Guilló-Sansano, Patrick Norman, Graeme Burt
Abstract
Power hardware-in-the-loop (PHIL) simulation leverages the real-time emulation of a large-scale complex power system, while also enabling the in-depth investigation of novel actual power components and their interactions with the emulated power grid. The dynamics and non-ideal characteristics (e.g., time delay, non-unity gain, and limited bandwidth) of the power interface result in stability and accuracy issues within the PHIL closed-loop simulations. In this paper, a compensation method is proposed to compensate for the non-ideal power interface by maximizing its bandwidth, maintaining its unity-gain characteristic, and compensating for its phase-shift over the frequencies of interest. The accuracy of power signals synchronization and the transparency of power transfer within the PHIL configuration are assessed by employing the error metrics. In conjunction with the frequency-domain stability analysis and the time-domain simulations, a case study is made to validate the proposed compensation method.