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Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis

Prince Kumar Singh, Kamalaksha Baral, Sanjay Kumar, Sweta Chander, Manas Ranjan Tripathy, Ashish Kumar Singh, Satyabrata Jit

2020Applied Physics A19 citationsDOI

Topics & Concepts

Materials scienceOxideOptoelectronicsNanotechnologyMetallurgyAdvancements in Semiconductor Devices and Circuit DesignSemiconductor materials and devicesIntegrated Circuits and Semiconductor Failure Analysis
Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis | Litcius