Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node
Daewon Ha, Yunsung Lee, Seung‐Hwan Yoo, W. Lee, M. H. Cho, Kicheon Yoo, S. M. Lee, Seungwon Lee, Masayuki Terai, Taewoo Lee, J.H. Bae, Kyoung-Jun Moon, Chang Kyung Sung, M. Hong, D. G. Cho, Kyoobin Lee, S.W. Park, K. Park, Bong Jin Kuh, Seok-Hun Hyun, S. J. Ahn, Jinook Song
Abstract
In order to sustain DRAM scaling trajectory below 10nm node, it is indispensable to adopt innovative cell structures, advanced processes and novel materials such as IGZO. In this paper, we will discuss promising candidates for IGZO-based DRAM cell architecture including vertical channel transistor (VCT), vertically stacked cell array transistor (VS-CAT) and capacitor-less two transistors (2T0C), and recent advances in key technologies including IGZO deposition, gate stack engineering, contact resistance, and so on.