Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling
Devin Verreck, A. Arreghini, F. Schanovsky, G. Rzepa, Zlatan Stanojević, F. Mitterbauer, C. Kernstock, O. Baumgartner, M. Karner, G. Van den bosch, M. Rosmeulen
Abstract
We present a physical modeling approach that explains the non-ideal ISPP slope in charge trap layer (CTL) flash memory and its impact on 3-D NAND vertical pitch scaling. First, we derive an expression for the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> change rate and use its field dependence to reproduce experimental vertical NAND ISPP slopes. Next, we implement a 2.5-D TCAD model based on these insights and show significant program voltage increase (>5V) in realistic 3-D NAND flash devices with scaling vertical pitch (down to 10nm). Finally, we evaluate high-k CTL and airgaps as mitigation measures at scaled pitch.