Hybrid Multisource Clock Tree Synthesis

Abstract

In physical design implementation, there are 3 main stages, placement and logic optimization, clock synthesis and routing optimization. Clock network synthesis is one of the important steps as it consumes at least 30% of total power budget. For high-performance blocks, the power consumption can be as high as 50% of total power budget. A good quality clock network not only will ease the timing convergence, reduce power consumption, also reduce the routing resource consumption. This paper will share the proposed hybrid multi-source clock tree synthesis that is suitable for full chip clock network planning as well as block level clock tree synthesis as needed. Hopefully, the sharing will benefits design community.

Topics & Concepts