A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application
Kishore Kumar Pakkirisami Churchill, Harikrishnan Ramiah, Alexander Choo, Gabriel Chong, Yong Chen, Pui‐In Mak, Rui P. Martins
Abstract
This brief proposes a 900-MHz novel CMOS-reconfigurable stack rectifier (RSR) implemented in a three-stage cross-coupled differential rectifier (CCDR) for battery-assist Internet-of-Things (IoT)/wireless sensor network (WSN) applications. A three-mode RSR is incorporated for an extended dynamic range (DR) input power level with a 100- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> load, fabricated in the 130-nm CMOS. The realized RSR achieves a wide DR power conversion efficiency (PCE) by reducing the ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> ) in the low-power zone (LPZ) achieved by reducing the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {th}}$ </tex-math></inline-formula> ) of the device and alternately increasing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {th}}$ </tex-math></inline-formula> in the high-power zone (HPZ) by implementing the proposed reconfigurable stack transistor technique along with the multithreshold voltage (MTV) technique. The circuit observes a measured result of 47.91% in peak PCE at an input power of −14 dBm by driving a 100- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> load. The proposed circuit also achieved 22.8 and 16.3 dB of DR with a PCE over 20% and 30%, respectively. Compared to other state-of-the-art designs, our work exhibits better DR and PCE.