GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking
Vijaypal Singh Rathor, Munesh Singh, Kshira Sagar Sahoo, Saraju P. Mohanty
Abstract
Logic locking has become a robust method for reducing the risk of intellectual property (IP) piracy, overbuilding, and hardware Trojan threats throughout the lifespan of integrated circuits (ICs). Nevertheless, the majority of reported logic locking approaches are susceptible to satisfiability (SAT)-based attacks. The existing SAT-resistant logic locking methods provide a tradeoff between security and effectiveness and require a significant design overhead. In this article, a novel gate replacement-based input-dependent key-based logic locking (IDKLL) technique is proposed. We first introduce the concept of IDKLL, and how the IDKLL can mitigate the SAT attacks completely. Unlike conventional logic locking, the IDKLL approach uses multiple key sequences (KSs) (instead of a single KS) as the correct key to lock/unlock the design functionality for all inputs. Based on this IDKLL concept, we developed several locked gates. Further, we propose a lightweight gate replacement-based IDKLL called GateLock that locks the design by replacing exciting gates with their respective IDKLL-based locked gates. The security analysis of the proposed method shows that it prevents the SAT attack completely and forces the attacker to apply a significantly large number of brute-force attempts to decipher the key. The experimental evaluation on International Symposium on Circuits and Systems (ISCAS) and International Test Conference (ITC) benchmarks shows that the proposed GateLock method completely prevents the SAT-based attacks and requires an average of 56.7%, 72.7%, and 87.8% reduced area, power, and delay compared to cascaded locking (CAS-Lock) and strong Anti-SAT (SAS) approaches.