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A low power single bit-line configuration dependent 7T SRAM bit cell with process-variation-tolerant enhanced read performance

Bhawna Rawat, Poornima Mittal

2023Analog Integrated Circuits and Signal Processing14 citationsDOI

Topics & Concepts

Process variationStatic random-access memoryVoltageComputer sciencePower (physics)Process cornersMemory cellCachePower consumptionElectronic engineeringElectrical engineeringComputer hardwareTransistorEngineeringParallel computingPhysicsQuantum mechanicsLow-power high-performance VLSI designVLSI and FPGA Design TechniquesParallel Computing and Optimization Techniques
A low power single bit-line configuration dependent 7T SRAM bit cell with process-variation-tolerant enhanced read performance | Litcius