High SFDR Current-Steering DAC With Splitting-and-Binary Segmented Architecture and Dynamic-Element-Matching Technique
Xingyuan Tong, Dong Liu
Abstract
This brief presents a current-steering digital-to-analog converter (DAC) with “4-bit splitting +8-bit binary” segmented topology. The proposed splitting decoding method can optimize the differential nonlinearity and output glitches of the DAC with a more simplified circuit scale than unary decoding. With a data-transmission topology, the splitting decoder has a low latency and accommodates fast synchronization control of current source switches. Moreover, the dynamic element matching (DEM) technique is used to suppress the harmonic distortion caused by the splitting current source mismatch. The DAC is designed using 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology and occupies an area of 452.82 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times491.76\,\,\mu \text{m}$ </tex-math></inline-formula> . With a 1.8 V analog supply and a 1.2 V digital supply, the DAC dissipates 12.2 mW at 500 MS/s. The spurious-free dynamic range of the DAC improves from 63.18 dB to 73.30 dB using DEM technique for an output signal of 8.30 MHz and by 8-10 dB within the Nyquist bandwidth.