Mechanical and Thermal Characterization Analysis of Chip-last Fan-out Chip on Substrate
Weijie Yin, Wei‐Hong Lai, Ying-Xu Lu, Karen Y.U. Chen, Hung-Hsien Huang, Tang-Yuan Chen, Chin‐Li Kao, C.-P Hung
Abstract
As the demand grow-up rapidly of the high-performance application such as computing, networking and cloud storage, the heterogeneous integration technology are developed and widely used to integrate multi-chips to connect Application Specific Integrated Circuit (ASIC) dies and High Bandwidth Memory (HBM) dies. The fan-out chip on substrate (FOCoS) is a solution to meet low cost, enhanced functionality and ideal for large package sizes with high I/O density. FOCoS chip last (FOCoS-CL) is meaning of wafer level process redistribution layers (RDLs) and polyimide layers assembled first, then multi-chips bonding on last step to complete molded fan-out chip which is potential integration of separately manufactured components into a higher level assembly. This study is to build a large size FOCoS-CL package finite element (FE) simulation model to evaluate the warpage, mechanical stress between die to die (D2D) and RDL trace broken risk analysis. The warpage validation between simulation and real package measurement was performed by advance Metrology Analyzer (aMA) system. The D2D gap is key location which has high coefficient of thermal expansion (CTE) mismatch to affect package reliability performance. Besides, thermal simulations are also to be investigated the heat dissipation performance of FOCoS-CL due to high power requirement. Furthermore, this research is focusing on mechanical and thermal characteristic analysis for large size FOCoS-CL and provides a design guideline of structure and Bill of Material (BOM) selection.