A 0.9-μA Quiescent Current High PSRR Low Dropout Regulator Using a Capacitive Feed-Forward Ripple Cancellation Technique
Tian Guo, Woobin Kang, Jeongjin Roh
Abstract
This article presents a high power supply rejection ratio (PSRR) low dropout (LDO) regulator with a low quiescent current. A low quiescent current capacitive feed-forward ripple cancellation (CFFRC) technique is proposed to cancel the power supply noise. With this technique, low power consumption is achieved via feed-forward capacitors and back-to-back pseudo-resistors bias. This design was fabricated using the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. The entire proposed LDO consumes a quiescent current of 0.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> . Compared with an LDO without enhancement, at the maximum load current of 200 mA, the measured PSRR has an enhancement of −22 dB at 1 MHz.