gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator
Guillem López-Paradı́s, Adrià Armejach, Miquel Moretó
Abstract
In recent years there has been a surge of interest in designing custom accelerators for power-efficient high-performance computing. However, available tools to simulate low-level RTL designs often neglect the target system in which the design will operate. This hinders proper testing and debugging of functionalities, and does not allow co-designing the accelerator to obtain a balanced and efficient architecture.
Topics & Concepts
DebuggingComputer scienceEmbedded systemComputer architectureArchitectureOperating systemArtVisual artsParallel Computing and Optimization TechniquesEmbedded Systems Design TechniquesInterconnection Networks and Systems