Performance Analysis Using Air Gap Defected Through Silicon Via: Impact on Crosstalk and Power
Maya Chandrakar, Manoj Kumar Majumder
Abstract
In the recent past, various fabrication-related defects such as electromigration-induced open/short faults, interfacial cracks, and thermal stress-induced leakage problems in through silicon via (TSV) have a major impact on the reliability and performance of a TSV-based 3-D integrated circuit (IC). Considering these facts, this article for the first time provides the equivalent resistance-inductance-conductance-capacitance (RLGC) modeling and performance analysis of air gap-defected TSVs in comparison with defect free vertical interconnect at 7 nm technology in order to address reliability concerns. Considering different manufacturing imperfections such as air cracks and void holes, the analytical equations are derived using defective parameters to analyze the feasibility and reliability of defected TSVs. Using a driver-via-load (DVL) setup, an equivalent T-type electrical modeling of cylindrical TSV is proposed considering the impact of different forms of air-cracked defects. Therefore, the propagation delay, power dissipation, power delay product, peak noise, and dynamic crosstalk are analyzed using a carbon nanotube field effect transistor (CNTFET) driver. Encouragingly, considering a partial air-cracked TSV, the peak noise is improved by 4.83% approaching toward defect-free condition.