A Systolic Array-Based Scheduling Strategy for Sparse CNN Accelerators
Guohe Zhang, Ruoyu Zhang, Ran Wang, Siyu Zhu
Abstract
Sparse convolutional neural network (CNN) accelerators face challenges such as low utilization of processing elements (PEs), low data reuse, and high hardware sparse index addressing cost during convolution operations. This brief proposes a new scheduling strategy for feature map sparse vectors and convolution kernel sparse vectors based on the systolic array and row stationary (RS) dataflow to overcome these problems. Our approach employs a design and implementation of a sparse convolution operation module based on systolic array, simulated comprehensively in Vivado using Virtex-7 VX690T version at a clock frequency of 150 MHz with a circuit power consumption of 8.15 W. We utilized the VGG-16 model to test and analyze the sparse convolution operation module. Results indicate an average effective operation utilization rate of PE computing units processed by the VGG-16 convolution layer at 65.34%.