An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder
S. Dhanasekar
Abstract
This article proposes a compact compressor adder of Vedic multiplication for an area-efficient FFT architecture. A standard multi-radix-24,22,23 FFT with a single-path delay feedback structure is considered. Vedic multipliers employ the Urdhva Tiryakbhyam method, which reduces redundant steps and generates parallel partial products. The proposed 4–2 compressor adders have been introduced inside the vedic multiplier to minimize carry delay and speed up the multiplication process. The vedic multiplier designed on the compressor adder saves power and gate count. The devised FFT algorithm is implemented using 45nm CMOS technology. Simulation results show a gate reduction of 21.5% and power consumption of 18.5%. The throughput had increased to 1.86 GS/s at 186 MHz compared to existing FFT architectures.