High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor With Top Gate to Drain Offset
Sunaina Priyadarshi, Mohammad Masum Billah, Hyunho Kim, Md. Hasnat Rabbi, Sadia Sayed Urmi, Suhui Lee, Jin Jang
Abstract
We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{\text {TG(Off)}}$ </tex-math></inline-formula> ) structure under dual-gate driving. The TFT shows an on/off current ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 10^{{7}}$ </tex-math></inline-formula> , subthreshold swing of 0.23 V/dec, and field-effect mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}$ </tex-math></inline-formula> ) of 14.6 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{\text {TG{(}Off{)}}}$ </tex-math></inline-formula> is 5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> , which is 30% reduction compared to the conventional DG TFT with no drain offset ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}=20.9$ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs). The Technology computer-aided design simulation indicates the electron concentration of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 10^{{16}}$ </tex-math></inline-formula> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> at the offset region near top gate insulator/a-IGZO interface when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{\text {TG{(}Off{)}}}$ </tex-math></inline-formula> is 5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> . The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.