A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS
Atharav Atharav, Behzad Razavi
Abstract
A wireline receiver consisting of a linear equalizer, a decision-feedback equalizer (DFE), a clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new circuit and architecture techniques that afford substantial power savings. Realized in 28-nm technology, the 56-Gb/s receiver has a bit error rate (BER) of less than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-12}$ </tex-math></inline-formula> for a channel loss of 25 dB at 28 GHz.
Topics & Concepts
DemultiplexerCMOSWirelineMultiplexerElectronic engineeringBit error rateEqualizerChannel (broadcasting)Computer scienceElectrical engineeringPower (physics)EngineeringTelecommunicationsPhysicsMultiplexingWirelessQuantum mechanicsAdvancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignPhotonic and Optical Devices