Study on 20 V LDMOS With Stepped-Gate-Oxide Structure for PMIC Applications: Design, Fabrication, and Characterization
Sue-Yi Chen, Benjamin S Liao, Jia-Ching Dong, Tim Wang, Shu-Len Wang, Hsiao-Ying Yang, Yin-Wei Peng, Shao-Chang Huang, Jon-Yiew Gan
Abstract
In this brief, a 20 V laterally diffused metal-oxide-semiconductor (LDMOS) device with the concept of stepped-gate-oxide (SGO) was fabricated with standard <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.15 ~\mu \text{m}$ </tex-math></inline-formula> BCD technology. Compared with the conventional shallow-trench-isolation LDMOS (STI-LDMOS), the SGO structure features a straight conduction path on a silicon surface, based on our past development experience, and therefore, an ON-resistance reduction of about 20% can be obtained. This brief demonstrated the LDMOS from a power-switching perspective, considering both optimization design and characterization aspects. The optimum device was demonstrated with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{ \mathrm{\scriptscriptstyle ON},sp}$ </tex-math></inline-formula> of 4.92 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , breakdown voltage (BV) of 23.8 V, and device figure of merit (FOM) of 20 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> -nC. By combining with optimum power stage design, the buck converter efficiency showed 93.88% at low load condition and 93.98% at high load condition, achieving an outstanding dc–dc converting performance.