An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology
Namik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Lyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Rui Wang, Matthew Loh, Alex Wang, M. Caresosa, Bo Zhang, Afshin Momtaz
Abstract
With the COVID–19 pandemic, the faster and more reliable connectivity solutions in data centers became the critical enabler technology of our daily activities. The current 50G data center switches have more than 500 lanes within a single chip solution. This massive integration puts strict restrictions on power/area consumption. Moreover, single-domain, low supply voltage operation is highly desirable for better package/board designs as well as improved silicon reliability with less aging impact. An ADC-based receiver with DSP equalization consumes higher power/area due to the time-interleaved ADC array and digital domain FFE/DFE taps. An analog CTLE/DFE-based transceiver with a single supply level is highly suitable for low power/area operation for high density IOs in data center switches. The TX driver supply level can be adjusted based on the application.