Characterization of Gate-Oxide Degradation Location for SiC MOSFETs Based on the Split <i>C–V</i> Method Under Bias Temperature Instability Conditions
Yumeng Cai, Cong Chen, Zhibin Zhao, Peng Sun, Xuebao Li, Manhong Zhang, Hui Wang, Zhong Chen, Hans‐Peter Nee
Abstract
Gate-oxide degradation has been one of the major reliability challenges of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. Comprehensive and accurate localization of gate-oxide degradation under bias temperature instability (BTI) conditions is important to improve the device reliability. The split <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C–V</i> [gate–source capacitance <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and gate–drain capacitance <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> )] method is proposed in this article to locate gate-oxide degradation. Moreover, a BTI automated characterization system integrated <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I–V</i> and split <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C–V</i> test is presented. The effect of gate-oxide degradation on threshold voltage and split <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C–V</i> under dc and ac BTI conditions is investigated and the degradation location is analyzed. Furthermore, the degradation simulation is conducted with technology computer aided design (TCAD) to reveal the mechanism. The results show that the different parts of split <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C–V</i> can characterize degradation location, the type, and energy level of traps. The acceptor traps near valence band and donor traps near conduction band cause gate-oxide degradation above the channel and junction field effect transistor (JFET) region in positive bias temperature instability (PBTI) and Negative Bias Temperature Instability (NBTI), respectively. In ac BTI, the gate-oxide degradation at the channel region is independent of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> polarity, while the opposite is true above JFET region. These findings help to improve the long-term operation reliability of gate oxide from the perspective of chip design and application.