Scaling effects on the microstructure and thermomechanical response of through silicon vias (TSVs)

Abstract

The dimensional scaling of through silicon vias (TSVs) is critical for the advancement of high-density 3D integration in future logic-on-logic and logic-on-memory computing architectures. Realizing such scaling demands an understanding of the thermomechanical response at the relevant length scales as both the microstructure and properties of the copper making up the majority of the TSV are dependent upon the size. In response, we examine here the residual stress development of the surrounding Si and microstructural evolution of Cu within TSVs as they are scaled from 5 to 1 μm diameter and thermally annealed. Using a combination of Raman spectroscopic and electron backscatter diffraction imaging accompanied by thermomechanical modeling, a non-monotonic trend between equivalent stress and TSV diameter is revealed. The non-monotonic trend is interpreted using an elastic thermomechanical model that accounts for competition between the global bending of the wafer and local Cu shrinkage. The elastic behavior is attributed, in large part, to a decrease in the mean grain size of Cu—and the accompanying increase in strength—that occurs with reduced TSV diameter. Thus, given the consistency of measured stress with the elastic model and the improved mechanical strength with decreased grain size, annealed Cu TSVs are deduced to remain more elastic compared to their larger counterparts as they scale from 5 to 1 μm.

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