Ferroelectric Vertical Gate-All-Around Field-Effect-Transistors With High Speed, High Density, and Large Memory Window
Weixing Huang, Huilong Zhu, Yongkui Zhang, Xiaogen Yin, Xuezheng Ai, Junjie Li, Chen Li, Yangyang Li, Lu Xie, Yongbo Liu, Jinjuan Xiang, Kunpeng Jia, Junfeng Li, Tianchun Ye
Abstract
Ferroelectric vertical gate-all-around field-effect-transistor (Fe-VGAAFET) suits a memory cell with a 5 nm technology node and beyond since it is less constrained by gate length, thereby providing sufficient space for the ferroelectric film compared with ferroelectric FinFET (Fe-FinFET) and ferroelectric lateral gate-all-around field-effect-transistors (Fe-LGAAFET). Also, Fe-VGAAFET achieves multilayer vertical stacking, which further increases the integrated density of devices. Here, we develop ferroelectric vertical sandwich gate-all-around field-effect-transistors (Fe-VSAFETs) with large memory windows (the maximum 2.3 V), high program/erase speeds (100 ns), and excellent retention properties using a self-aligned high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> metal gate process. Furthermore, vertical nanosheet devices with two channel thicknesses of approximately 16 and 42 nm and nanowire devices with a channel diameter of 30 nm were successfully fabricated, and excellent device characteristics were obtained.