16.5 A 13b 0.005mm<sup>2</sup> 40MS/s SAR ADC with kT/C Noise Cancellation
Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun
Abstract
As with any ADC with a front-end S/H, the SAR ADC suffers from a fundamental SNR challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor has to be sufficiently large (e.g. 3pF for a 13b ADC with 2V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> swing). This, however, makes it very costly to design the ADC input driver and the reference buffer. The input driver and the reference buffer are the bottleneck nowadays. Their power, area, and design complexity can be an order of magnitude higher than the SAR ADC core.
Topics & Concepts
Successive approximation ADCNoise (video)CapacitorComputer scienceBottleneckSampling (signal processing)SwingElectronic engineeringPhysicsElectrical engineeringEngineeringTelecommunicationsAcousticsDetectorEmbedded systemArtificial intelligenceVoltageImage (mathematics)Analog and Mixed-Signal Circuit DesignLow-power high-performance VLSI designAdvancements in Semiconductor Devices and Circuit Design