Review of Vedic Multiplier Using Various Full Adders
A. Abdul Hayum, S. Chinnapparaj, G. Sujatha, G. Thamarai Selvi, Mohd Naved, P Mohanraj
Abstract
The complexity of the chip is increasing as the advances in VLSI technology leads to the accumulation of more and more devices on a single chip. Since the chip has high density, the power dissipated in the chip or the amount of the heat produced is also increased resulting in the low power CMOS VLSI designs. In digital computer systems and digital signal processors, multiplication is one of the basic reckoning processes. This paper reviews the 2 by 2 vedic multiplier design using various high speed and low power adders.
Topics & Concepts
Very-large-scale integrationAdderMultiplier (economics)CMOSComputer scienceChipDigital signal processingDigital signal processorMultiplication (music)Electronic engineeringComputer hardwareEmbedded systemEngineeringMathematicsTelecommunicationsCombinatoricsEconomicsMacroeconomicsLow-power high-performance VLSI designQuantum-Dot Cellular AutomataAdvancements in Semiconductor Devices and Circuit Design