A Study on the Comprehensive Analysis of Electro Migration for the Nano technology trends
Sankararao Majji, Tulasi Radhika Patnala, Manohar Valleti, Chandra Sekhar Pasumarthi, Srilekha Kothapalli, Santoshachandra Rao Karanam
Abstract
As technology advances towards lower nodes, chip industry facing severe challenges from its counterpart node with the narrow interconnects. Density of current becomes more affected with these higher device currents and increasing on-chip temperature. The interconnect reliability and their possible degradation from electro migration is a severe concern. Perhaps the problem of carrier migration requires attention from fabrication industry at higher technology nodes, more specifically electro migration becomes a severe concern at 28nm and below. Beside power dissipation, speed of the IC and area on the chip, electro migration also becomes severe at technology nodes 28nm and below. In this brief a comprehensive analysis of electro migration and inter connect parasitic are described for various trends of nanometer technology.