Reduced‐Complexity LDPC Decoding for Next‐Generation IoT Networks
Muhammad Asif, Wali Ullah Khan, H. M. Rehan Afzal, Jamel Nebhen, Inam Ullah, Ateeq Ur Rehman, Mohammed K. A. Kaabar
Abstract
Low‐density parity‐check (LDPC) codes have become the focal choice for next‐generation Internet of things (IoT) networks. This correspondence proposes an efficient decoding algorithm, dual min‐sum (DMS), to estimate the first two minima from a set of variable nodes for check‐node update (CNU) operation of min‐sum (MS) LDPC decoder. The proposed architecture entirely eliminates the large‐sized multiplexing system of sorting‐based architecture which results in a prominent decrement in hardware complexity and critical delay. Specifically, the DMS architecture eliminates a large number of comparators and multiplexors while keeping the critical delay equal to the most delay‐efficient tree‐based architecture. Based on experimental results, if the number of inputs is equal to 64, the proposed architecture saves 69%, 68%, and 52% area over the sorting‐based, the tree‐based, and the low‐complexity tree‐based architectures, respectively. Furthermore, the simulation results show that the proposed approach provides an excellent error‐correction performance in terms of bit error rate (BER) and block error rate (BLER) over an additive white Gaussian noise (AWGN) channel.