A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry
S. KONNO, Yuichi Miyahara, Kazuki Sobue, Koichi Hamashita
Abstract
This paper presents a THD improved SAR ADC without any calibration or DEM for DAC mismatch. The proposed SAR ADC has a new method of cancellation of all even order distortions caused by a DAC mismatch. In order to improve THD performance, we focused on symmetric property in the DAC mismatch. This method just needs very simple circuits with a few extra clocks.
Topics & Concepts
Successive approximation ADCCalibrationTotal harmonic distortionComputer scienceElectronic engineeringSpurious-free dynamic rangeComparatorPhysicsEngineeringElectrical engineeringVoltageDynamic rangeQuantum mechanicsAnalog and Mixed-Signal Circuit DesignCCD and CMOS Imaging SensorsAdvancements in Semiconductor Devices and Circuit Design