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A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology

Mohammad Moradinezhad Maryan, Majid Amini‐Valashani, Seyed Javad Azhari

2021Circuits Systems and Signal Processing33 citationsDOI

Topics & Concepts

PMOS logicNMOS logicCMOSLeakage (economics)NAND gateLogic gatePass transistor logicTransistorStandby powerXNOR gateSpiceElectronic engineeringElectrical engineeringEngineeringVoltageXOR gateComputer scienceEconomicsMacroeconomicsLow-power high-performance VLSI designSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit Design
A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology | Litcius