The AMD “Zen 2” Processor
David Suggs, Mahesh Subramony, Dan Bouvier
Abstract
The “Zen 2” processor is designed to meet the needs of diverse markets spanning server, desktop, mobile, and workstation. The core delivers significant performance and energy-efficiency improvements over “Zen” by microarchitectural changes including a new TAGE branch predictor, a double-size op cache, and a double-width floating-point unit. Building upon the core design, a modular chiplet approach provides flexibility and scalability up to 64 cores per socket with a total of 256 MB of L3 cache.
Topics & Concepts
Computer scienceScalabilityCacheMulti-core processorModular designOperating systemEmbedded systemFlexibility (engineering)CPU cacheMicroarchitectureEfficient energy useComputer architectureFloating-point unitMobile processorWorkstationParallel computingMobile deviceComputer hardwareFloating pointMobile WebMobile technologyMathematicsStatisticsElectrical engineeringEngineeringSecurity and Verification in ComputingParallel Computing and Optimization TechniquesAdvanced Memory and Neural Computing