Buried Power SRAM DTCO and System-Level Benchmarking in N3
Shairfe Muhammad Salahuddin, Manu Perumkunnil, E. Dentoni Litta, Anshul Gupta, Pieter Weckx, Julien Ryckaert, M.-H. Na, A. Spessot
Abstract
The increased metal resistance degrades both the performance and write margin of SRAM circuits in sub-10nm nodes. This paper utilizes buried power distribution as SRAM performance and write ability booster in 3nm node. BPR-SRAM offers up to 34.5% read speed and 498.6mV write margin improvement over conventional SRAM. Gem5 system simulator predicts up to 28.2% performance gain with server-processor having BPR-SRAM in L2 and L3 cache as compared to the baseline.
Topics & Concepts
Static random-access memoryCacheComputer scienceCPU cacheBenchmark (surveying)Random access memoryBooster (rocketry)Embedded systemOperating systemComputer hardwareEngineeringGeodesyAerospace engineeringGeographyLow-power high-performance VLSI designAdvanced Memory and Neural ComputingSemiconductor materials and devices