A 213-233 GHz ×9 Frequency Multiplier Chain with 4.1 dBm Output Power in 40nm Bulk CMOS
Ruibing Dong, Shinsuke Hara, Issei Watanabe, Satoru Tanoi, Tatsuo Hagino, Akifumi Kasamatsu
Abstract
A ×9 frequency multiplier chain with 3-dB bandwidth of 213-233 GHz was implemented in 40nm bulk CMOS. It realized 4.1 dBm peak output power without using power combining. Two frequency triplers are cascaded to realize ninth time multiplication of the input frequency. A center-taped transformer and a notched filter are used to suppress the 1st and 2nd harmonics of tripler, respectively. A J-band power amplification block, which is similar with injection locked oscillator, was design to enhance the output power and realized harmonics suppression. Comparing with the expected 9th harmonic, the 4th and 6th harmonics are lower than 67 dB and 35 dB respectively. The other harmonics are not observed in experiment.