7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE
Xiongshi Luo, Xuewei You, Zhenghao Li, Hamed Mosalam, Dongfan Xu, Taiyang Fan, Hongchang Qiao, Wentao Zhou, Hongzhi Wu, Liping Zhong, Patrick Yin Chiang, Quan Pan
Abstract
With the exponential growth of artificial intelligence systems and cloud computing, next-generation wireline transceivers are aiming for data rates of 800GbE/1.6TbE, requiring 224Gb/s per lane. Potential 224Gb/s long-reach (LR) solutions [1] include: 1) ADC/DSP-based schemes; 2) PAM-6/PAM-8/OFDM modulation schemes; or 3) PAM-4 retimers with embedded CDRs and equalizers. While all of the above schemes are based on differential signaling, there has been recent interest in single-ended schemes, such as 2D/3D interposer, UCIe, or memory [2, 3, 4]. Compared to differential signaling schemes, single-ended systems can achieve doubled pin efficiency and higher-density IOs. For example, state-of-the-art single-ended links from [4] achieve excellent energy/bit and pin density, but currently are limited to 50Gb/s/wire and a distance of 1.2mm (−5dB insertion loss (IL)). In this work, we propose a $4 \times 224$ Gb/s single-ended transceiver front-end with up to 29dB equalization for high-pin-density and long-distance scenarios. Furthermore, for IL larger than 30dB, another promising scheme may consist of one low-power XSR/VSR SerDes or retimer, the proposed single-ended transceiver frontend, and single-ended channels, as shown in Fig. 7.5.1 (top).