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Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission

Maged ElAnsary, Jianxiong Xu, José Sales Filho, Gairik Dutta, Liam Long, Camilo Tejeiro, Aly Shoukry, Chenxi Tang, Enver G. Kilinc, Jaimin Joshi, Parisa Sabetian, Samantha Unger, José Zariffa, Paul D. Yoo, Roman Genov

2021IEEE Journal of Solid-State Circuits46 citationsDOI

Abstract

An active probe and microstimulator SoC for interfacing with peripheral nerves is presented. It performs 64-channel artifact-tolerant neural recording, cuff imbalance compensation by impedance sensing, and neurostimulation for the closed-loop operation. Each recording channel is a second-order opamp-less <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC that consumes 140 nW and occupies 0.01 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area in 130 nm CMOS. The single-loop <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> architecture achieves second-order noise shaping with two passive integrators. To the best of our knowledge, this yields the lowest power and area of any second-order <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC and the lowest FOM (fJ/conv. step) of any passive second-order <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC (27 fJ/conv. step). The SoC uniquely performs multi-modal input signal recording: voltage (for neural recording) and current (for impedance sensing) are measured concurrently using frequency multiplexing. The SoC also features a 60 MHz energy-efficient inductive powering link and a 600 MHz RF data communication link. The prototype is validated <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in vivo</i> in the rat sciatic nerve for electroneurogram (ENG) sensing and the correction of impedance-imbalance in cuff electrodes.

Topics & Concepts

Computer scienceAlgorithmMathematicsAdvanced Memory and Neural ComputingNeuroscience and Neural EngineeringAnalog and Mixed-Signal Circuit Design
Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission | Litcius