A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz

Claudio Nani, Enrico Monaco, N. Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabrizio Giunco, Daniel Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Lucas Vignoli, Enrico Temporiti, S. Scouten, S. Jantzi

202414 citationsDOI

Abstract

We present a 60GS/s 7b 64-way Time Interleaved (TI) ADC with Analog Front End that features a non binary Partial Loop Unrolled (LU) SAR SubADC architecture which enables optimum comparator noise and power trade off. Comparator offsets among comparators of each SubADC are calibrated in background without analog hardware overhead by detecting patterns in the SAR output decisions. Fabricated in 5nm technology, the prototype AFE and ADC delivers 34.3dB SNDR till 32GHz and draws 109.3mW from 0.9V supply.

Topics & Concepts

Successive approximation ADCComputer scienceLoop (graph theory)Electronic engineeringPhysicsElectrical engineeringCapacitorEngineeringVoltageMathematicsCombinatoricsAnalog and Mixed-Signal Circuit DesignNeuroscience and Neural EngineeringCCD and CMOS Imaging Sensors