A 14 GHz Integer-N Sub-Sampling PLL With RMS-Jitter of 85.4 fs Occupying an Ultra Low Area of 0.0918 mm<sup>2</sup>
Dipan Kar, Soumen Mohapatra, Md Aminul Hoque, Deukhyoun Heo
Abstract
This paper presents a 14 GHz sub-sampling PLL (SSPLL) with its phase noise analysis for Ku-band wireless transceivers. The performance enhancement of the phase-locked loop (PLL) over single-stage PLL in terms of jitter and power consumption is theoretically presented and verified with measured results. The proposed capacitor multiplier reduces the size of the loop filter capacitor by 28 times. The active capacitor VCO decreases the out-band phase noise while consuming less power. Fabricated in a 65 nm CMOS process with a core active area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.0918~mm^{2}$ </tex-math></inline-formula> , the SSPLL operates at 1.2 V supply achieving 13.2-14.8 GHz tuning range, 85.4 fs integrated jitter at 14 GHz, 8.42 mW power consumption, and −252.12 dB figure-of-merit (FoM). The measured results in-band and out-band phase noises of −108.6 dBc/Hz at a 1 MHz offset and −128.9 dBc/Hz at a 10 MHz offset, respectively.