Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer

Zisong Wang, Peiyi Zhao, Tom Springer, Congyi Zhu, Jaccob Mau, Andrew Wells, Yinshui Xia, Lingli Wang

2023IEEE Transactions on Very Large Scale Integration (VLSI) Systems28 citationsDOI

Abstract

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs.

Topics & Concepts

Flip-flopTransistorCMOSCritical path methodComputer scienceTransmission gatePower–delay productLow-power electronicsPower (physics)Computer hardwareParallel computingPower consumptionElectrical engineeringAdderVoltageEngineeringPhysicsSystems engineeringQuantum mechanicsLow-power high-performance VLSI designAdvancements in Semiconductor Devices and Circuit DesignParallel Computing and Optimization Techniques