A High-Speed and Energy-Efficient Multi-Bit Cyclic ADC Using Single-Slope Quantizer for CMOS Image Sensors
Ji-Yong Jeong, Junbo Shim, Seong‐Kwan Hong, Oh‐Kyong Kwon
Abstract
This brief proposes a high-speed and power-efficient multi-bit cyclic analog-to-digital converter (MC ADC) for CMOS image sensor applications. The proposed 13-bit MC ADC, which uses a 4-bit single-slope (SS) quantizer as a sub-ADC, resolves the sampled input voltage, followed by the cyclic SS quantization operation that repeatedly produces and quantizes the residue voltage. It operates in only seven phases to resolve 13-bit, thus achieving high conversion speed. Moreover, the 4-bit SS quantizer employs a simple and power-efficient structure that includes only the analog circuits of an operational amplifier and a comparator. A test chip with the proposed MC ADC was fabricated using a 0.18-μm standard CMOS process technology. The measurement results show that the proposed MC ADC achieves a differential nonlinearity of +0.5/-0.54 LSB and an integral nonlinearity of +1.7/-2.8 LSB. In addition, the maximum signal-to-noise-and-distortion ratio and the effective number of bits are measured to be 73.14 dB and 11.86-bit, respectively. The measured power consumption per channel is only 87 μW at a sampling frequency of 781 kHz. Moreover, the figure of merit (FoM), which includes the power consumption per channel, row line time, and ADC resolution, is only 13.6 fJ/conversion, achieving the best FoM among the compared works. Therefore, the proposed MC ADC is suitable for CMOS image sensor applications requiring high conversion speed and low power consumption, such as digital single-lens reflex cameras and ultra-high-definition television broadcast cameras.