A Hybrid Continuous-Time Incremental and SAR Two-Step ADC With 90.5-dB DR Over 1-MHz BW
Yanchao Wang, Siladitya Dey, Tao He, Lukang Shi, Jiawei Zheng, Manjunath Kareppagoudr, Yi Zhang, Kazuki Sobue, Koichi Hamashita, Koji Tomioka, Gábor C. Temes
Abstract
This letter presents a hybrid continuous-time (CT) incremental and SAR two step ADC to provide high resolution with low oversampling ratio (OSR) and Nyquist conversion rate. The first CT incremental ADC (IADC) stage achieves large bandwidth, low thermal noise, and power consumption. The residual error of the CT IADC is extracted at the last integrator output and transferred to the 2nd SAR for further conversion. In this architecture, only the mismatch between the cascade of analog integrators (CoIs) and digital decimation filter transfer functions causes 1st stage quantization noise leakage, which is much smaller than that in the multistage noise-shaping (MASH) architecture. The ADC is fabricated in the AKM 180-nm CMOS process with 1.8-V supply voltage. It achieves a DR of 90.5 dB, SNR/SFDR/SNDR of 82.5/85/80.5 dB, and Schreier figure of merit (FoMs) of 165.5 dB over 1-MHz bandwidth (BW).