A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping for Energy-Efficient RRAM-Based In-Memory Computing
Weier Wan, Rajkumar Kubendran, Bin Gao, Siddharth Joshi, Priyanka Raina, Huaqiang Wu, Gert Cauwenberghs, H.‐S. Philip Wong
Abstract
The energy efficiency of RRAM-based in-memory matrix-vector multiplication (MVM) depends largely on the output sensing mechanism. We design a novel voltage-mode sensing configuration with differential-row weight mapping that achieves a 3.6x improvement in energy per multiply-accumulate (MAC) at the same read voltage compared to current-mode sensing, and avoids the nonlinear source-line dynamics issue that occurs in conventional voltage-mode sensing. We verify the MVM performance of our scheme by performing measurements using a RRAM array monolithically integrated with CMOS voltage-mode neurons. We compare the effects of weight normalization on MVM accuracy under two different weight mapping schemes, and provide guidance in selecting the scheme based on weight sparsity and consistency of the L-1 weight norm across the columns.