A 1.8-nW, −73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes
Cheng-Ze Shao, Shih-Che Kuo, Yu‐Te Liao
Abstract
This article presents a nanowatt CMOS voltage reference using self-biased and capacitively coupled schemes for improving the power supply rejection ratio (PSRR) and settling time without power-intensive auxiliary amplifiers and bias circuits. The chip was fabricated in a 0.18- μm CMOS process. With the proposed schemes, the design can achieve a 1% settling time of 0.2 ms and a -73.5-dB PSRR at 100 Hz while only consuming 1.8 nW. The average temperature coefficient of 15 chips is 62 ppm/°C in a temperature range from -40 °C to 130 °C. The average voltage at 20 °C is 0.26 V, while the standard deviation is 1.1 mV and 3 σ accuracy is 0.43%.
Topics & Concepts
Power supply rejection ratioCMOSSettling timeElectrical engineeringVoltageMaterials scienceAmplifierTemperature coefficientVoltage referenceElectronic engineeringOptoelectronicsPhysicsEngineeringStep responseControl engineeringAnalog and Mixed-Signal Circuit DesignAdvancements in Semiconductor Devices and Circuit DesignRadio Frequency Integrated Circuit Design