Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design
Devenderpal Singh, Shalini Chaudhary, Basudha Dewan, Menka Yadav
Abstract
Abstract This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel. For the analysis, three different channel structures are used: (a) tri-layer stack channel (TLSC) (Si–SiGe–Si), (b) double layer stack channel (DLSC) (SiGe–Si), (c) single layer channel (SLC) (Si). The I − V characteristics, subthreshold swing (SS), drain-induced barrier lowering (DIBL), threshold voltage ( V t ), drain current ( I ON ), OFF current ( I OFF ), and ON-OFF current ratio ( I ON / I OFF ) are observed for the structures at a 20 nm gate length. It is seen that TLSC provides 21.3% and 14.3% more ON current than DLSC and SLC, respectively. The paper also explores the analog and RF factors such as input transconductance ( g m ), output transconductance ( g ds ), gain ( g m / g ds ), transconductance generation factor (TGF), cut-off frequency ( f T ), maximum oscillation frequency ( f max ), gain frequency product (GFP) and linearity performance parameters such as second and third-order harmonics ( g m2 , g m3 ), voltage intercept points (VIP 2 , VIP 3 ) and 1-dB compression points for the three structures. The results show that the TLSC has a high analog performance due to more g m and provides 16.3%, 48.4% more gain than SLC and DLSC, respectively and it also provides better linearity. All the results are obtained using the VisualTCAD tool.