Layer-to-Layer Endurance Variation of 3D NAND Flash Memory
Md Raquibuzzaman, Md Mehedi Hasan, Aleksandar Milenković, Biswajit Ray
Abstract
The block size of flash memory chips has increased significantly with the introduction of 3D NAND technology, causing "big-block" management issues in storage systems. In this paper, we characterize endurance of individual pages in a block and show that pages in the bottom and top layers exhibit lower endurance than pages in the middle layers. This variation in endurance among pages can cause severe underutilization of big memory blocks. We find that erase threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> ) variation between the layers is the root cause for the observed endurance variation.
Topics & Concepts
NAND gateVariation (astronomy)Block (permutation group theory)Layer (electronics)Flash (photography)Computer scienceFlash memoryComputer hardwareLogic gateMaterials scienceMathematicsAlgorithmPhysicsNanotechnologyGeometryAstrophysicsOpticsAdvanced Data Storage TechnologiesMagnetic properties of thin filmsSemiconductor materials and devices