A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS
G. Gangasani, D. Hanson, D. Storaska, Hao Xu, M. Kelly, M. Shannon, M. Sorna, M. Wielgos, P. B. Ramakrishna, Stephen Shi, S. Parker, U. K. Shukla, W. Kelly, Wei-Zen Su, Z. Yu
Abstract
Hyperscale data center applications are driving the need for high bandwidth, high throughput per chip-edge, ultra-low-power serial-IO solutions over extremely short-reach (XSR) MCM connections. This paper demonstrates an MCM chiplet with > 1.6Tb/s throughput over a range of CEI-112G-XSR standard-compliant channels using a fully integrated and adaptive PAM-4/NRZ transceiver supporting data rates from 9.8-to-113Gb/s. Key features of the transceiver include an architecture designed to lower TX signal launch amplitude and RX data path gain to relieve power/area/bandwidth constraints. It achieves required equalization while minimizing residual-ISI and quantization errors for improved performance. It has the capability for RX-driven dynamic adaptation of TX and RX equalization settings for seamless bring-up over hundreds of lanes in an MCM application, as well as to track supply and temperature drifts. It also features programmable TX-FFE roaming taps to boost performance in case of severe reflections and includes precision clock phase generation and correction.